Direct answer
Choosing an architecture by an unqualified switching or noise claim can leave the frequency plan unusable. A microwave synthesizer generates programmable frequencies from a reference using direct analog synthesis, DDS, PLL techniques or a hybrid. The overview compares those families; the mechanism sections then focus on PLLs. In a basic locked PLL, output frequency is N times the detector reference, and its in-band reference-noise contribution rises by 20·log₁₀(N) dB. That is output multiplication, not the noise effect of a standalone divider. Compare coverage, usable steps, spurs and time to the required output tolerance under stated conditions.
Key takeaways
- The loop bandwidth decides which noise source you inherit at which offset.
- In a locked PLL, output multiplication by N raises the in-band reference-noise contribution by 20·log₁₀(N) dB; ideal standalone division reduces it.
- A basic integer-N PLL links output steps to the detector frequency; fractional-N permits finer steps but needs its fractional-spur behavior checked.
- With a YIG oscillator as the VCO, the loop drives the FM coil while the main coil parks the band.
- Lock time and spurious performance both trade against loop bandwidth, in opposite directions.
A frequency synthesizer is a programmable frequency source. First distinguish the architecture families below; a finished unit may combine them. The following loop explanation concerns PLL synthesis, with N measured relative to the phase-detector reference after any reference division.
Direct analog, DDS and PLL: choose the governing constraint
These are architecture families, not interchangeable performance guarantees. A finished synthesizer can combine them, so first ask which block sets the output coverage, smallest usable step and settled response.
| Family | How the frequency is formed | When to investigate it | What needs evidence |
|---|---|---|---|
| Direct analog | Switch, multiply, divide and mix reference-derived frequencies | Repeatable transitions or coherence are central to the frequency plan | Selected conversion path, filtering, unwanted mixing products and the time to the required output tolerance |
| Direct digital synthesis (DDS) | Clocked phase accumulation and amplitude conversion followed by a DAC and reconstruction filtering | Fine programmable steps and controlled phase changes are important | Clock quality, usable output band, DAC images and in-band spurs for the actual tuning words |
| PLL synthesis | Feedback locks a tunable oscillator to a divided or fractional relationship with a reference | Programmable coverage must be combined with a stable reference | Loop bandwidth, oscillator range, reference/detector noise, spurs and the full settling criterion |
The direct-analog description follows Giga-tronics’ High Speed Frequency Synthesis application note. ADI’s MT-085 DDS tutorial explains the digital path, sampling images and spurious mechanisms; MT-086 covers PLL behavior. The comparisons are qualitative because a family name does not supply a guaranteed switching time or spur limit.
Where it sits in the chain
A synthesizer is a frequency source with a programmable output. In a receiver it is the local oscillator; in a transmitter, the exciter; in test equipment, the signal source. Everything downstream — the mixer or converter, the IF chain — inherits its phase noise and its spurious content, which is why the synthesizer specification tends to bound system performance rather than merely contribute to it.
The loop
Four elements, and each one owns a specification you will later argue about.
The reference sets long-term accuracy and drift, and its phase noise is what the output carries close to the carrier. An OCXO is quieter and more stable than a TCXO, larger, and needs warm-up.
The phase detector compares at a frequency f_PD. Its own noise floor, multiplied up by the division ratio, sets the close-in floor of the whole synthesizer.
The loop filter sets the loop bandwidth, and therefore the crossover between the two noise regimes. This is the single most consequential design choice in the loop.
The oscillator — the VCO in the general case, a YIG oscillator in wideband microwave designs — contributes the noise outside the loop bandwidth.
The two relationships worth internalising
PLL output multiplication raises the reference contribution. For the basic locked relation F_out = N × F_PD in ADI MT-086, figure 1, the in-band reference phase deviation is multiplied by N. The contribution rises by 20·log₁₀(N) dB. Example, assumed N = 1,000: the increase is 60 dB, not a prediction of total output noise. Ideal independent division has the opposite sign; Giga-tronics AN-GT167A, section II.B, page 3 discusses the multiplication/division relationship.
Loop bandwidth chooses your noise source. Inside the loop bandwidth the output tracks the reference, so you get reference noise plus 20·log(N). Outside it, the loop no longer corrects fast enough and you get the oscillator’s own noise. A wide loop pulls more of the curve down to the reference — good, if the reference is quiet and N is small. A narrow loop leaves more of the curve to the oscillator — good, if the oscillator is a low-noise YIG source.
There is no universally correct answer, which is why reading the phase noise plot matters more than reading a single number. Ask which offsets your system integrates over, then ask where this synthesizer’s crossover sits relative to them.
PLL subtypes: integer-N and fractional-N
| Criterion | Integer-N | Fractional-N |
|---|---|---|
| Step constraint | F_PD in the basic single-loop output relation | Fractional average ratio permits finer steps at a given F_PD |
| Noise comparison | Record carrier, offset, N, reference and locked state | Record the same conditions and fractional mode |
| Spur check | Reference-related tones and hardware nonidealities | Reference-related tones plus fractional-sequence effects |
| Transition check | Measure actual endpoints and final tolerance | Use the same endpoints and tolerance; no automatic speed advantage |
ADI MT-086, Frequency Synthesis and Fractional-N sections explains these constraints. Multi-loop and DDS-assisted PLLs combine blocks rather than form another peer of DDS or direct analog synthesis.
Takeaway: Compare PLL modes at the same carrier, offset and settling criterion before claiming a noise or speed advantage.
When the VCO is a YIG oscillator
When a synthesizer uses a dual-coil electromagnet YIG oscillator as its VCO, check three additional requirements.
The loop drives the FM coil, not the main coil. The main coil parks the oscillator near the target; the loop corrects from there through the fast, narrow FM winding. The mechanism is in how YIG oscillators work.
Lock time gains a magnetic term. Before the loop can capture, the main coil has to settle — a millisecond-scale magnetic process, not a loop-bandwidth one. Quoted lock times should say whether they include that.
Verify noise outside the loop. Compare the actual carrier, offsets, driver and lock state. Broad product-range envelopes do not establish the performance of one locked assembly.
Key specifications
| Parameter | What it means | What it constrains |
|---|---|---|
| Frequency range | Span of programmable output | How many sources the frequency plan needs |
| Step size / resolution | Smallest programmable increment | Channel plan; and, in integer-N, everything else |
| Phase noise | ℒ(f) at stated carrier, offsets, reference and lock state | Receiver reciprocal mixing and noise budget |
| Spurious | Discrete tones, reference and fractional | Spurious responses — these do not integrate like noise |
| Lock / switching time | Time to settle within tolerance after a command | Hop rate; sweep rate; test throughput |
| Reference input | External 10 MHz in, or internal OCXO/TCXO | System coherence and long-term accuracy |
| Harmonics | Output multiples of the carrier | Filtering needed ahead of a broadband mixer |
Parameter meanings are general to the device class. Values vary by architecture and vendor; work from the specific part's datasheet.
Two of those deserve emphasis because they are routinely conflated.
Spurious is not phase noise. A spur is a deterministic tone. It does not integrate the way broadband noise does, and one spur landing in a critical offset can matter more than several decibels of clean noise elsewhere.
Lock time is not one number. Time to reach a coarse tolerance and time to settle to a tight one can differ by an order of magnitude, and with a YIG-based source the magnetic settling may or may not be included. Ask what tolerance the quoted figure refers to.
Selection criteria
Advantages and limitations
Advantages. Programmable frequency with the reference’s long-term accuracy. Predictable noise behaviour once the loop bandwidth is known. With a YIG VCO, a single unit covering an octave or more at genuinely low noise.
Limitations. Every architecture trades resolution, lock time and spurs against each other; none of the three is free. Reference quality bounds close-in performance no matter what the oscillator does. YIG-based units inherit the size, power draw and magnetic sensitivity of a magnetically tuned source.
Typical applications
Receiver and exciter local oscillators in radar, electronic warfare and SIGINT, where wide coverage and low reciprocal mixing both matter. Automated test equipment, where switching time drives throughput. SATCOM up- and downconverters, where long-term stability and coherence dominate. Spectrum monitoring, where source noise and the tracking preselector’s loss need a shared receiver budget.
Testing and integration notes
Use this record for each switching test, including the worst required step. “Locked” and “ready for use” need not have the same endpoint.
| Test field | Required condition | Recorded result |
|---|---|---|
| Start / stop / direction | Fill: frequency endpoints and command time | Fill: trace and control version |
| Readiness criterion | Fill: frequency error, residual FM, phase and blanking | Fill: time each limit is met |
| Tracking filter timeline | Fill: filter command time and tolerance | Fill: source and filter readiness together |
| Noise / spurs | Fill: carrier, offsets, search band and reference plane | Fill: locked noise plot and spur map |
| Reference / environment | Fill: internal or external reference, level, temperature, warm-up | Fill: reference-loss and reacquisition behavior |
Use YIG filter guidance for tracking constraints and phase-noise guidance for the spectral record.
Takeaway: Accept the full transition to the system’s tolerance, including the reference and filter conditions.
Synthesizer IC or finished module: assign the integration work
A chip purchase leaves more of the implementation with your team; a module can include some of that implementation, but the boundary must be read from its documentation. ADI’s PLL and DDS tutorials show why the clock/reference, filters, supplies and surrounding circuits are part of the result. The table is a responsibility checklist, not a claim that every module integrates every block.
| Work item | Included / external owner | Document or acceptance result |
|---|---|---|
| Reference and loop / reconstruction filters | Fill: supplied blocks and design owner | Fill: revision and required external circuits |
| Power, layout and installation | Fill: board or module installation owner | Fill: supply, grounding and connector evidence |
| Programming and calibration | Fill: command / calibration owner | Fill: startup sequence and version |
| Noise and spur evidence | Fill: assembly measurement owner | Fill: carrier, offsets, reference, temperature and lock state |
A useful RFQ states frequency coverage and resolution, output level and load, phase-noise offsets, spur search range, transition endpoints and settling tolerance, reference input, environment, interfaces and required records. Align the measurement conditions using the engineering comparison checklist and phase-noise guidance before treating two offers as equivalent.
Related guides
- YIG oscillators — requirements when the loop uses a wideband YIG VCO
- How YIG oscillators work — why the loop drives the FM coil
- Understanding phase noise — reading ℒ(f) rather than a headline figure
- RF signal chain — where a source sits relative to mixers and filters
- Component sourcing and quality — obsolescence and traceability on long-life parts
Frequently asked questions
Why does the PLL output have more reference phase noise?
Within a locked PLL's bandwidth, the output tracks N times the detector reference, giving a 20·log₁₀(N) dB increase in that reference-noise contribution. An ideal independent divider instead reduces input phase noise by 20·log₁₀(N) dB at the same offset, until added noise or a floor matters.
What sets the lock time?
Principally the loop bandwidth — a wider loop corrects faster. With a YIG oscillator there is a second term, because the main coil has to move the oscillator into the loop's capture range first, and that is a magnetic settling time rather than a loop time.
Where do reference spurs come from?
The phase detector operates at a discrete comparison frequency, and imperfect suppression of that process leaves discrete tones at multiples of it. Fractional-N adds its own spurs from the division sequence, which is the price of decoupling step size from the comparison frequency.
Why use a YIG oscillator rather than a varactor VCO in the loop?
For wide coverage with low noise outside the loop bandwidth. A YIG oscillator covers an octave or more at low phase noise, so one loop replaces several. Where the requirement is fast switching over a narrow span, a varactor VCO is the better VCO.
Sources
- Electromagnetic YIG Oscillators (Wide Tuning Range) — Micro Lambda Wireless Accessed August 28, 2026.
- Phase Noise Measurements with a Real-Time Spectrum Analyzer, chapter 7 — Berkeley Nucleonics Accessed August 28, 2026.
- The Role of the Preselector Filter in a Receiver Front End — RF Essentials Accessed August 28, 2026.
- MT-085: Fundamentals of Direct Digital Synthesis, figures 1–2 — Analog Devices Accessed October 8, 2026.
- MT-086: Fundamentals of Phase Locked Loops, figure 1 and synthesis sections — Analog Devices Accessed October 8, 2026.
- AN-GT167A: High Speed Wide Band Frequency Synthesis, sections II.B–III — Giga-tronics Accessed October 8, 2026.
